Designing and training a lightweight machine learning model to detect, classify, and alert on malicious RF jamming attacks (Flood, Pulse, Sweep, Tone) in real-time. Building an optimized C++ inference pipeline intended for integration as an open-source security plugin for Meshtastic mesh networks.

Engineered a custom feature extraction pipeline utilizing low-pass filtering to isolate low-frequency spectral rhythms, enabling the model to generalize across unknown attack vectors while achieving over 94% validation accuracy. Implemented custom firmware-level probability summing and sliding-window debounce logic to maintain a near-zero false positive rate in chaotic background RF environments.

Building a containerized backend service that leverages deep learning to automatically separate raw audio into isolated stems and transcribe them into multi-track MIDI files for studio production.

Engineered the core asynchronous worker using Docker Compose to orchestrate Redis, Celery, and PyTorch safely. Implemented custom extraction logic using pretty_midi to map isolated vocals, basslines, and harmonic chord stems into distinct, editable MIDI channels.

Developed a low-latency, high-precision 3D localization framework integrating a dual-polarized antenna array with optimized spatial spectrum estimation algorithms as a Master Thesis. Engineered a hardware-software data pipeline that streams raw digital I/O phase metrics over serial data formats directly into parallel math processing engines, bypassing standard local network layers.

Evaluated spatial correlation matrices across multi-element arrays to isolate signals from structural calibration defects. System optimizations balanced the physics of wave orientation and Constant Tone Extension (CTE) sampling bounds against energy limits. The finalized execution implements real-time covariance eigenstructure routing to drop multi-path phase errors.

As an undergrad project I designed and implemented a scalable, high-throughput Input Arbiter in Verilog to eliminate idle cycles when routing multi-queue inputs to a single shared resource. Built an optimized architectural layout that groups lines and segments logic across distinct data paths, decentralized controllers, and a global finite state machine.

Developed a multi-stage combinational matrix layout to bypass standard sequential verification loops. Integrated predictive blocking pipelines utilizing synchronized control flags to prevent early buffer starvation during active packet bursts. Validated physical timing, resource footprints, and multi-stream data paths within Vivado simulation engines.